1. Field of the Invention
The present invention relates to an image sensor, more specifically, to a complementary metal oxide semiconductor (CMOS) image sensor and manufacturing method thereof.
2. Description of the Related Art
Conventionally, an image sensor, as a kind of semiconductor device, transforms optical image into electrical signal, which can be generally classified into a charge coupled device (CCD) and a CMOS image sensor.
A CCD comprises a plurality of photo diodes arranged in the form of matrix to transform optical signal into electrical signal, a plurality of vertical charge coupled devices (VCCDs) formed between the photo diodes to transmit charges generating in each photo diode in a vertical direction, a plurality of horizontal charge coupled devices (HCCDs) for transmitting charges transmitted from each VCCDs in a horizontal direction, and a sense amp for sensing charges transmitted in the horizontal direction to output electrical signals.
It has been generally known that CCDs have complicated operational mechanism, and high power consumption. In addition, its manufacturing method is very complicated, because multiple steps of photolithography processes are required in its fabrication. Especially, it is difficult to integrate a CCD with other devices such as control circuits, signal processing circuits, analog/digital converter, etc., in a single chip. Such disadvantage of CCD hinders miniaturization of products.
In order to overcome above described disadvantages of CCDs, CMOS image sensors have been recently developed as the oncoming generation of image sensor. A CMOS image sensor generally comprises MOS transistors formed in a semiconductor substrate by CMOS fabrication technologies. In a CMOS image sensor, the MOS transistors are formed relative to the number of unit pixels, along with peripheral circuits such as control circuits, signal processing circuits, and the like. CMOS image sensors employ a switching mode that MOS transistors successively detect the output of each pixel.
More specifically, CMOS image sensors comprise a photo diode and MOS transistors in each pixel, thereby successively detecting electrical signals of each pixel in a switching mode to express a given image.
The CMOS image sensor has advantages such as low power consumption and relatively simple fabrication process. In addition, CMOS image sensors can be integrated with control circuits, signal processing circuits, analog/digital converter, etc., because of using CMOS manufacturing technologies, which enables miniaturization of products.
CMOS image sensors has been widely used in a variety of applications such as digital still camera, digital video camera, and the like.
Meanwhile, CMOS image sensors can also be classified into 3T, 4T, 5T types, etc., according to the number of transistors. The 3T type of CMOS image sensor comprises one photo diode and three transistors, and the 4T type comprises one photo diode and four transistors. Here, a layout of unit pixel in a 4T type of CMOS image sensor is configured as follows.
FIG. 1 is a circuit diagram of a conventional 4T type of CMOS image sensor. FIG. 2 is a layout of unit pixel in the conventional 4T type of CMOS image sensor. And, FIG. 3 is a cross-sectional view illustrating a photo diode and a transfer transistor of a conventional CMOS image sensor, in view of I-I′ line in FIG. 2.
As shown in FIG. 1, each unit pixel 100 of the conventional CMOS image sensor comprises a photo diode (PD or 10) functioning as a photoelectric transformer, and four transistors including a transfer transistor 20, reset transistor 30, driver transistor 40, and select transistor 50. In addition, the output terminal (referred to as “OUT”) of the each unit pixel 100 is electrically connected to a load transistor 60.
In FIG. 1, the reference symbol “FD” represents a floating diffusion region, “Tx” represents a gate voltage of the transfer transistor 20, “Rx” represents a gate voltage of the reset transistor 30, “Dx” represents a gate voltage of the driver transistor 40, and finally “Sx” represents a gate voltage of the select transistor 50.
As shown in FIG. 2, in the conventional CMOS image sensor, an active region is defined in a portion of each unit pixel, and an isolation layer is formed in the remaining portion of each unit pixel except for the active region. One photo diode PD is formed in a large portion of the defined active region, and gate electrodes 23, 33, 43, and 53 of four transistors are respectively formed to be overlapped with other portion of the active region.
The gate electrode 23 constitutes the transfer transistor 20. The gate electrode 33 constitutes the reset transistor 30. The gate electrode 43 constitutes the driver transistor 40. And, the gate electrode 53 constitutes the select transistor 50.
Here, dopant ions are implanted in the active region where each transistor is formed, except for the portion of active region below each gate electrodes 23, 33, 43, and 53, to form source and drain regions of each transistor.
FIG. 3 is a cross-sectional view of the photo diode and the transfer transistor, in the above-described structure of the conventional CMOS image sensor.
Referring to FIG. 3, a P− type epitaxial layer 11 is formed on a P++ type semiconductor substrate, using epitaxial growth process.
The gate electrode 23 for the transfer transistor 20 in FIG. 1 is formed on the epitaxial layer 11, interposing the gate insulating layer 21. The first and second insulating sidewalls 29 and 30 are formed on both sides of gate electrode 23.
In addition, a N− type diffusion region 28 and a P0 type diffusion region 35 are formed in photo diode region of epitaxial layer 11. The P0 type diffusion region 35 is formed over the N− type diffusion region 28 in the photo diode region. Source/drain diffusion regions, consisting of lightly doped drain (LDD) region 26 having a N− conductivity type and a high concentration of N+ diffusion region 32, is formed in the transistor region of epitaxial layer 11.
Here, “P−” type diffusion region represents a doped region by a low concentration of P-type dopants, a “P0” type diffusion region represents a doped region by a middle concentration of P-type dopants, and a “P+” type diffusion region represents a doped region by a high concentration of P-type dopants, and finally a “P++” type diffusion region represents a doped region by a higher concentration of P-type dopants. Similarly, “N−” type diffusion region represents a doped region by a low concentration of N-type dopants, and a “N+” type diffusion region represents a doped region by a high concentration of N-type dopants.
FIGS. 4a to 4i are cross-sectional views illustrating a conventional method for manufacturing a CMOS image sensor.
Referring to FIG. 4a, a P− type epitaxial layer 11 is formed on the semiconductor substrate such as single crystalline silicon having a heavy concentration and a first conductivity type (i.e., P++ type).
Here, the epitaxial layer 11 functions to form a deep and wide depletion region in the photo diode region. Thereby, the ability of a low-voltage photo diode for gathering photoelectrons can be improved, and also the light sensitivity can be improved.
Next, a gate insulating layer 21 and a conductive layer (e.g., a heavy doped polysilicon layer) are deposited on the entire surface of the epitaxial layer 11, in successive order. The conductive layer is selectively patterned using photolithography and etching processes, thus forming the gate electrode 23.
The gate insulating layer 21 can be formed using thermal oxidation process or chemical vapor deposition (CVD) process. In addition, the gate electrode 23 can further comprise a silicide layer thereon.
Next, as shown in FIG. 4b, the gate electrode 23 is thermally oxidized so that a thermal oxidation layer 24 is formed on the exposed surface of the gate electrode 23.
Referring to FIG. 4c, a first photoresist layer 25 is applied over the entire surface of the substrate including the gate electrode 23, and then it is patterned using exposure and development processes, thus covering the photo diode region and exposing the transistor region where source/drain regions will be formed.
Using the first photoresist pattern 25 as a mask, a low concentration of N-type dopant ions are implanted in the exposed transistor region to form the N− type diffusion region 26.
As shown in FIG. 4d, after removal of the first photoresist pattern 25, a second photoresist layer 27 is applied over the semiconductor substrate, and then it is patterned using exposure and development processes, thus exposing the photo diode region.
Then, using the second photoresist pattern 27 as a mask, a low concentration of N-type dopant ions are implanted in the photo diode region at an ion implantation energy of 100 keV˜500 keV, thus forming the N− type diffusion region 28. Hereinafter, the N− type diffusion region 28 is also referred to as “PDN region.”
Meanwhile, the N− type diffusion region 28 of the photo diode region is preferably formed in a diffusion depth more than that of the N− type diffusion region 26 of source/drain regions, using higher implantation energy.
As shown in FIG. 4e, after removing the second photoresist pattern 27, the oxide layer 29a and the nitride layer 30a are formed over the entire surface of the substrate by CVD, e.g., LPCVD (Low Pressure Chemical Vapor Deposition) process.
Continuously, an etch back process is preformed on the oxide layer 29a and the nitride layer 30a to form the first and second insulating sidewalls 29 and 30 on both sides of the gate electrode 23, as shown in FIG. 4f. 
As shown in FIG. 4g, a third photoresist layer 31 is formed over the entire surface of the substrate, and then it is patterned by exposure and development processes to cover the photo diode region and expose the transistor region.
Continuously, using the third photoresist pattern 31 as a mask, a high concentration of N-type dopant ions are implanted in source/drain regions to form the N+ type diffusion region 32.
As shown in FIG. 4h, after removing the third photoresist pattern 31, a fourth photoresist layer 34 is applied over the entire surface of the substrate, and then it is patterned by exposure and development processes to expose the photo diode region.
Then, using the fourth photoresist pattern 34 as a mask, a middle concentration of P-type dopant ions are implanted in the photo diode region to form the P0 type diffusion region 35 over the N− type diffusion region 28. Hereinafter, the P0 type diffusion region is also referred to as “PDP region.”
Here, the photo diode can comprise only the N− type diffusion region 28, without the P0 type diffusion region 35.
As shown in FIG. 4i, after removing the fourth photoresist pattern 34, heat-treatment process (e.g., rapid thermal process) is performed on the substrate to activate dopants in the N− type diffusion region 26, the P0 type diffusion region 35, the N− type diffusion region 28, and the N+ type diffusion region 32.
However, in the above-described conventional CMOS image sensor, there are problems as follows. Namely, as shown in FIG. 4h, the P-type dopant ions are rarely implanted in the portion of the photo diode region below the first and second insulating sidewalls 29 and 30, because the P-type dopants ions are blocked by the sidewalls 29 and 30 during the implantation process for the P0 type diffusion region 35. As a result, charges accumulated in the photo diode region may leak out in the region where the P-type dopant ions are blocked.